Dates and Venues / Agenda / Registration / Access information
Date & Venue
Date: Monday, March 12th, 2018
Venue: Akihabara, Tokyo, Japan;
Akihabara Convention Hall 5th floor: Room 5C http://www.akibahall.jp/data/access_eng.html
Workshop Motivations
The performance evolution of high-performance computing (HPC) and data analytic systems has been governed in the past by integration improvements in the CMOS technology. This trend is expected to continue until the mid-2020s when CMOS features will reach 5-7 nm. In the following period, performance progress for CMOS-based integrated circuit devices will no longer come mostly from higher levels of integration, and other approaches will be needed.
The convergence of several technologies makes HPC-relevant FPGA-powered systems attractive. These technologies are (1) new FPGA system-on-chip devices featuring multicore CPUs, FPGAs, and thousands of hardened floating-point data signal processing blocks; (2) robust compiler technologies capable of targeting heterogeneous systems; and (3) tools for transforming intermediate representation objects into a hardware description language such as VHDL and Verilog, available from research groups and from vendors. These, combined with the push toward expressing parallelism and data dependencies specified by parallel programming APIs (e.g., OpenMP, OpenCL), opens up FPGA-based solutions for serious exploration in scientific simulations and data analytics.
Workshop Objectives
The workshop will pursue several objectives. First, it will review the state of the art in this domain internationally. Second, it will help understand trends in FPGA technologies and better identify and understand open problems and challenges. Third, it will provide a unique opportunity to identify and to discuss potential collaborations.
Agenda (tentative)
Talk title will be updated soon.
| 10:00-10:15 | Opening: Welcome Remarks Taisuke Boku (University of Tsukuba) |
| 10:15-11:00 | Keynote: FPGA Datacenters for HyperScale HPC [Abstract] Andrew Putnam (Microsoft) |
| 11:00-11:30 | Data-Flow Hardware Optimization by Design Space Exploration [Abstract] Kentaro Sano (Riken) |
| 11:30-11:45 | Break |
| 11:45-12:15 | Portable HPC with FPGAs should not be this hard: What to do about it Martin Herbordt (Boston University) |
| 12:15-12:45 | Case Studies: HPC Acceleration with Intel FPGAs [Abstract] Brad Kadet (Intel Programable Solutions Group) |
| 12:45-14:15 | Lunch |
| 14:15-14:45 | Working toward performance portability for FPGAs in High Performance Computing Jeff Vetter (ORNL) |
| 14:45-15:15 | Key software challenges in FPGA-enabled heterogeneous platforms [Abstract] Kazutomo Yoshii (ANL) |
| 15:15-15:45 | Developing applications with OmpSs@FPGA [Abstract] Xavier Martorell (BSC) |
| 15:45-16:00 | Break |
| 16:00-16:30 | Computation/Communication offloading to FPGA with GPU [Abstract] Taisuke Boku (University of Tsukuba) |
| 16:30-17:45 |
Panel: Reconf500: Can we join the 500 club? [Abstract] Moderator: |
| 17:45-18:00 | Closing: Taisuke Boku (University of Tsukuba) |
Workshop Registration
Online registration has been closed. There are very few seats still remained, and please come directly to the workshop venue if you want to make on-site registration. However we cannot guarantee your seats at that time.
Workshop registration is free of charge. We will stop accepting applications when seats are filled.
We are planning to have a reception after workshop. It is about JPY4,000 charge by your own. Please remark it in the following registration form if you want to join. The reception fee will be collected at on-site registration desk. Please understand that we cannot handle any credit-card.
Online Registration: here
Workshop Organization
The workshop is organized to maximize interactions and discussions among participants. It will feature talks from key players of FPGA and scientific simulation and data analytics domains. Considerable time will be allotted during coffee breaks, lunch and dinner to discuss potential collaborations.
Logistics
Details about the workshop will be available on the workshop webpage that we will communicate soon. The venue is the Akihabara Convention Hall: http://www.akibahall.jp/data/access_eng.html
Workshop Organizers
Workshop co-chair:
Taisuke Boku (University of Tsukuba)
Franck Cappello (Argonne National Laboratory)
Sponsors
Workshop Sponsor: JST-CREST Project “Research and Development on Unified Environment of Accelerated Computing and Interconnection for Post-Petascale Era”
Supported by Center for Computational Sciences, University of Tsukuba
Contact
iwfh2018[at]ccs.tsukuba.ac.jp