Title： Early single node and multinode experience with the Knight’s Landing processor
Speaker： Prof. Peter Boyle (Edinburgh University)
Venue： Center for Computational Sciences, International Workshop Room
We discuss work to develop a new lattice QCD code base, Grid, targeting many multicore processor architectures with various forms of vector instructions. In particular we discuss recent efforts to optimise Grid for the new AVX512 instruction set on the Knights Landing processor. We also discuss the growing impact of interconnect performance on Lattice QCD codes, and compare the Cray Aries, Mellanox EDR and Intel Omnipath architectures. The performance curve for lattice QCD codes on such systems, after optimisation can be seen to be a simple and reasonably easily predictable function of the cache sizes, memory and network bandwidths.
contact: pr [at] ccs.tsukuba.ac.jp ([at] -> @)